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TC3299A preliminary dat a sheet pcm c i a bu s i n t e r f a c e log i c an d dr i v er s p c m c ia bu s tc 3299 t r ansm i t an d recei v e co nt r o l lo g i c ex t e r nal sram dma buff er c ont r o l l o g i c m anchest e r enc o der a nd de c o der a u i i n te rf a c e t p in te rf a c e phy s i c al m edi um aut o - m ux bl ock di agram o f tc 3299a 93c 56/ 66 fo r ci s & n ode id ( t c 3299 a o p tion ) ethernet pcmcia controller + combo t r ansceiver features 1/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30 pcmcia 2.01 bus interface. u s e s e rial eeprom 93c56/93c66 to s t ore cis. ne2000 compatible. ieee 802.3 compatible. ns8390 register compatible controller. endec, utp, aui, and included. auto media select between aui and utp. led support for activity and link. 100-pin lqfp package. low power cmos process. TC3299A for utp and aui interface. general description the tc3299 a ( epcc) is designed to r educe p a rt s count and cost for easy implement a t ion of pcmcia csma/cd lo cal area networks. the TC3299A is the in tegratio n o f the en tire bus in te rface for pcmcia bu s and whic h it include s etherne t controller , ma nchester encoder/decoder , 10baset function and aui in terface. it complies with ieee 802.3 st andards. tc 3299a is co mp atible to ns8390 controller ' s register and nove ll ne2000 industry ether net st andard . t o s t ore c i s, TC3299A needs eeprom 93c56/6 6 in pcmcia lan card to reduce p a r t cost. physic al media 10baset , aui inter f ace are fully automa t ic detectio n . led driver for link and other activities are also provided. tc32 99a is desi gne d for conventio na l pcmcia lan ca rd with aui cabl e con n e c ting to external mau. tc32 99a provid e s both utp and aui interface for maximum flexibility . 10baset fun c tional blo c k include s re ceiver an d transmitter , collision, l oop back, jab b e r and li nk integrity . the polarity detection/ corre c tion blocks are also defined as in the st andard. TC3299A use s analog pha s e lock loop method for the manchester encoding a nd the decoding me thod is specified b y the ieee 8 02.3 speci f ica t ion in the 10mbit/sec tr ansmission s e ction. a collision de tect translator an d diagnos tic loopback cap ability are also included in the TC3299A. block diagram confidential.
TC3299A preliminary dat a sheet t a ble of content s features ....................................................................................................................... ....................................... 1 general description ............................................................................................................ ................................ 1 block diagram .................................................................................................................. ................................... 1 t a ble of cont ent s .............................................................................................................. ................................. 2 pin conf igurat ion .............................................................................................................. .................................. 3 1 pin description ................................................................................................................ ............................ 4 2 func tional description ......................................................................................................... ....................... 7 2.1 power on conf iguration ....................................................................................................... 9 3 conf igurat ion regis t ers ........................................................................................................ .................... 1 1 3.1 epcc core r egis t ers ........................................................................................................ 12 4 abs o lut e max i mum rat i ngs ....................................................................................................... ............... 2 5 5 s t andard t e s t condit ions ....................................................................................................... ................... 2 5 6 d. c. characteris t ics .......................................................................................................... ...................... 2 5 7 phy s ical dimens ions ............................................................................................................ ..................... 2 6 confidential. 2/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet pin configuration 1 2 3 4 5 6 7 8 9 1 0 11 1 2 13 14 1 5 1 6 17 18 19 2 0 2 1 22 23 2 4 2 5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 w e * s a 0 s a 1 s a 2 s a 3 s a 4 s a 5 s a 6 s a 7 s a 8 s a 9 a c l e d g n d n c d i d o n c n c v c c c e 1 * i o r * i o w * o e * r e g * g n d ma 14 ma 3 ma 2 ma 1 ee cs sd 1 5 sd 1 4 sd 1 3 sd 1 2 sd 1 1 sd 1 0 sd 9 sd 8 gnd io16 * inpa ck * int * vc c nc gnd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 v c o i c d + 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 wa i t * sd 0 sd 1 sd 2 sd 3 sd 4 sd 5 sd 6 sd 7 rs t vc c gn d td l y + td - td l y - td + rd+ rd- av d d rx + 46 47 48 49 50 rx - ag n d tx + tx - ll e d 76 77 78 79 80 ma 7 ma 6 ma 5 ma 4 vc c TC3299A 100pin lqfp c d - x 1 m d 1 m a 1 2 m w * m a 1 0 m a 9 m a 8 m d 0 c s 0 * m r * m a 0 m a 1 3 m a 1 1 x 2 g n d v c c m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 confidential. 3/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 1 pin description pin no. sy mbol i/o description isa bus interface pins 2-1 1 s a 0 - s a 9 i these a ddre ss sig nal lin es of p c m c ia bus a r e use d to sele ct a register to be read or written and attribute memory enable. 27-34 93-86 sd0-sd7 sd8-sd15 i/o i/o regi ster access, with dma inac tive, sd0-sd7 p i ns are u s ed t o read/ write re gister dat a. s d 8-s d 1 5 pin s are invalid durin g this st ate . remote dm a bus cy cl e, sd0-s d 1 5 pin s cont ain p a cket dat a . direction of transfer is depended on remote read/write. 35 rst i re set pin. rst is active high an d pla c ed epcc i n a re set m o d e immediately . duri ng falli ng edg e, the epcc co ntrolle r load s th e configuration from md0-7, ma0-13. 2 6 w a i t * o this pin is set low to insert wait st ates during remote dma transfer . 2 4 r e g * i reg* is an a c tive low inpu t used to dete r mine whe t he r a lost access i s to attribute memory (the first 1k) or to common memory (above 1k). if reg* is s e t to low the acc e s s is to attribute memory , while reg* i s set to high th e access is to commo n memory . reg* is also asserte d low for all accesses to the TC3299A ( s i o regist ers. 21 ior* i rea d s t rob e : s t robe f r om host to re ad intern al regi sters o r rem o t e dma read. 22 iow* i w r ite s t ro be: s t robe from host to write internal regi sters or rem o t e dma write. 23 oe* i ho st memo ry read strob e . the attribut e memo ry ca n be re ad whe n oe* and reg* are both at low st ate. while fo r co mmon me mo ry to be a c ce ssed, oe* sh ould b e set to lo w st ate and reg* should set to high st ate. o e * r e g * attribute memory low low common memory low high 1 we* i ho st memory write strobe. af te r powe r reset, if tc32 99a is config ure d to memory write e nabl e, then 2 type s of mem o ri es a r e writte n a s defined below: w e * r e g * attribute memory low low common memory low high 9 6 i n p a c k * o a ctive low signal, assert ed if the ho st access tc32 99a interna l register or remote dma read cycle. 95 io16* o io16* is driven by epcc to support host 16 bit s access cycle. 9 7 i n t * o interrupt:indicates that t he epcc re quire s ho st attention af te r reception, transmission or completion of dma transfer . 20 ce1* i card ena ble 1, are a c tive low si gnal s d r i v en by the ho st. these sig nal s provide a ca rd sele ct ba sed on an a d d re ss decod e (de c od e by th e hos t). confidential. 4/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet pin no. sy mbol i/o description memory interface pins 6 5 - 5 8 md0-7 i/o whe n rst i s ina c tive these pi ns can be use d to acce ss exte rna l memory . wh en rst is a c tive configu r ation is load ed with the dat a value on md0-md7 pins. 79-70 81 82-84, 69 ma4-13 ma14 ma3-1, ma0 i/o whe n rst i s ina c tive th ese pins driv e the memo ry addre s s b u s durin g dma a c cess cycle. whe n rst i s active co nfig uration i s loa d e d with the dat a value on ma0-ma13 pins. 68 mr* o memory bus read: s t rob e s dat a from the buf fer memory into th e epcc via the memory dat a bus. 67 m w * o memory bus w r ite: s t robes dat a from the epcc into the externa l buf fer memory via the memory dat a bus. 66 cs0* o buf f er ram chip select, active low . 85 eecs o eeprom chip select. it is asserted when to access eeprom. 16 do i connected to eeprom dat a output pin. 15 di o connected to eeprom dat a input pin. pin no. sy mbol i/o description clock interface pins 54 x1 i cryst a l or external oscillator input:20 mhz 55 x2 o cryst a l feedback output:used in cryst a l connection only . pin no. sy mbol i/o description netw ork interface pins 41,39 td+/- o 10baset dif f erential transmit drivers. 38,40 tdl y +/- o 10baset wave predist ortion control dif f erential output s. 42,43 rd+/- i 10baset dif f erential receive input port. 51 vcoi i filter input for dat a recover analog pll. 50 lled o link integral led driv er . during link loss, output high. during loading eeprom dat a, used as serial clock to the eeprom. 12 acled o whe n po we r on reset, this pin must st ay at high l e vel. otherwi se , TC3299A will enter internal test mode. active led:(default) ma8 is open, wh en power re set. it function s a s active indication led driver . cled: ma8 pull down during powe r reset. it works as collisi on le d driver . pin no. sy mbol i/o description netw ork interface pins(TC3299A option) 4 5 , 4 6 r x + / r x - i 10base5, receiver input p a ir to controller . 4 8 , 4 9 t x + / t x - o 10base5, t r ansmit output p a ir from controller . 52,53 cd+/cd- i 10base5, collision input p a ir to controller . confidential. 5/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet pin no. sy mbol i/o description pow e r supply pins 19,36,57,8 0,98 13,25,37,5 6,94, 100 44 47 vcc gnd a v dd agnd +5v dc is required. it is sugge sted t hat a deco u p ling ca p a citor b e connected between vcc and gnd. power for analog phase lock loop circuit of epcc. confidential. 6/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 2 functional description the epcc controlle r is a highly integra t ed jumperl e ss config urabl e ethernet co ntrolle r . it integrate s the function of the following blocks: TC3299A ethernet controller core and media access control logic. 1. pcmcia 2.0 bus inte rface con t ainin g a ll logics req u i r e to con n e c t the t c 329 9 a co re to a p a cket buf fer ram and the pcmcia bus. 2. serial eprom interfaces, which loads ethernet id and configuration registers into the epcc. 3. physical media interface cont ains encoder/decoder with a 10baset t w isted pair interface. i/o port address mapping this is comp atible with novell ( s ne20 00. the base i/o addre s s of epcc controlle r is configured by config uratio n registe r s (ei t her upon po wer up or writ ing to this register by sof t wa re ). at that a ddre s s the following structure appears. base + 00h bas e + 0fh TC3299A core registers base +10h base + 17h dat a t r ansfer port base + 18h bas e + 1fh reset port the regi sters within this area are 8 bit s wide, b u t t he dat a tra n sfe r port is 16 bit s wide. by accessing th e dat a tra n sfe r port (usin g i/o instructio n s ) the user can tran sfe r d a t a to or fro m the epcc controller ( s internal memory . the epcc controller ( internal memory map is as shown below . d 1 5 d 7 d 0 0000h prom 0 0 1 f h reserved 4000h 7fffh 8k 16 buf f er ram epcc core ( s memory map prom location location content s 00h ethernet address 0 01h ethernet address 1 02h ethernet address 2 03h ethernet address 3 confidential. 7/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet prom location location content s 04h ethernet address 4 05h ethernet address 5 06-0dh reser ved 0e,0fh 57h 10-15h ethernet address 0-5 16-1dh reser ved 1e-1fh 42h det a ils of prom map epcc cont roller actually has a 64k a ddre s s rang e but only d o e s p a rtial de codi ng o n th ese devices . the prom d a t a is mirrore d at all decod es up to 400 00h an d the entire map i s repeate d at 8000 0h. t o acce ss eithe r the prom o r the ram th e user mu st initiate a remote dma transfer between the i/o port and memory . remote read/w rite cache: the epcc controlle r inclu des 4 wo rd s ca che intern a lly . on a remote read the epcc co ntro ller moves dat a from external me mory buf fer to th e internal cache buf fer; the epcc moves dat a contin uou sly until the cache bu f f er is full. on a remote write the sy stem can write s dat a into the cach e buf fer until the 4 words cache buf fer is full. pcmcia cis s t ructures & decode function: the t c 32 99 a sup p o r t s a c cess to 1k of attribute m e mory . attrib ute memo ry i s defin ed by the pcm c ia st an dard to be comp ri sed of the card ( s informatio n st ructu r e a nd four 8 - bi t s ca rd configu r ati on regi ste r s. these four registe r s a r e cont aine d in the tc32 99a . the attribute memory (o nly even address can be accessed) map for a pcmcia card is shown below . 7 0 (reserved) 3feh (reserved) 3fch ccr1 (TC3299A) 3f ah ccr0 (TC3299A) 3f8h reserved 3f0h-3f6h card ' s information structure 2eeh 02 00 card configuration registers 0(r/w) (ccr0) 7 6 5 4 3 2 1 0 r e s e t x x ioen x x x x x x pj 1 pj 0 reset : when this bit is set 1, a sof t ware reset to TC3299A. ioen : when this bit is set 1, the i/o operation is enabled. confidential. 8/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet pj1,0 : i f m a 1 2 i s n ( t p u l l e d lo w d u r i n g p o w e r o n r e s e t , d e sp ite o f th e value o f pj1 , 0, tc 32 99 a resp onse to i/o access at the i/o base address 300h, 320h, 340h, 360h. otherwise, i/o base map as below: p j 1 p j 0 i / o b a s e m a p 0 0 300h 0 1 320h 1 0 340h 1 1 360h pj1,0 : reserved configuration registers 1 ? (ccr1) 7 6 5 4 3 2 1 0 x x x x x x x x x x x x ireq x x ireq : controller interrupt st atus x x : r e s e r v e d 2.1 pow e r on configuration the epcc c ontroller configures it self af ter a rst si g nal is app lied . when a po wer-on-reset occurs the epcc contro ller latches th e va lues on the config urat ion pins and uses these to configure the in ternal registers and op tions. in te rnally these pins cont ain pull-up resist ance. if thes e configuratio n pins are unconnected the defau lt lo gic will be ap plied. the co nf igura t ion re gisters are lo aded from the memor y dat a bus when rst goes inactive. a power-on-reset also caus es the epcc controll er t o load the in t e rnal p r om store f r om the eeprom, whi c h ca n t a ke up to 3 ms. this occu rs af ter co nfig -re g s (co n figuratio n regi sters? ) have completed. if eeconfig i s high (ma9 pull down ) the configurati on dat a loaded on the fal li ng edge of rst will be overwritten by the dat a read from the s e rial eeprom . regardless of the leve l on eeconfig the prom store will always be loaded with dat a from the serial eeprom during the time specified as eeload. figure 1 shows how the r eset circuitry operates. vcc reset regload eeload the epcc controller us ers an 93c56/66, the programmed c ontent s of the eeprom is s hown as following. d 1 5 d 0 ...... cis byte n cis byte n-1 . . . . . . 1 6 h . . . . . . . . . . . . . . . . 1 4 h . . . . . . . . . . . . . . . . 12h cis byte 3 cis byte 2 confidential. 9/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet d 1 5 d 0 10h cis byte 1 cis byte 0 0fh not used config. c 0 e h c o n f i g . b c o n f i g . a r e s e r v e d r e s e r v e d 0 8 h 4 2 h 4 2 h 0 7 h 5 7 h 5 7 h 0 4 h r e s e r v e d r e s e r v e d 03h reserved bit (0) : 8 bit enable bit (7:1) : res e rved 02h e ( net address 5 e ( net address 4 01h e ( net address 3 e ( net address 2 00h e ( net address 1 e ( net address 0 eeprom programming map **03 h bit(0):if ma1 1 is pull ed low du rin g powe r on re set and thi s bit is set high . TC3299A can wo rk at ne2000 ' s 8-bit mode. s t oring and loading configuration from eeprom: if the eeconfig is set high (ma9 p u ll low) duri n g boot up, th e epcc con t roller ' s conf iguratio n is determined by the eeprom, before the prom dat a is read the co nfigura t ion dat a is st ored wi thin the address 0e h of the eeprom ' s add ress sp ace. configuration register a and b are located in the address 0eh. t o write this config uratio n into the eepro m, the user ca n prog ra m registe r in epcc ' s add ress 02 h of p age 3. this operation will work regardless of the level on eeconfig . confidential. 10/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 3 c o n f i g u r a t i o n r e g i s t e r s configuration register a (r/w) t o pre v en t an y accident a l write o f th is re gister , it is ? h i dden ? beh ind a pre v iously unused register . register 0ah in the epcc controller ' s page 0 of regis t ers was previously reserved on a read. now configura t io n register a can be read at that address and can be written to by following a read to 0ah with a write to 0ah. if any other encc co ntroll er regi ste r acce sses t a ke place betwe e n the read an d the write then the write to 0ah will access the remote byte count register 0. 7 6 5 4 3 2 1 0 x x f r e a d x x x x x x x x x x x x fread :the encc c ontr o ller su ppo rt s 4 word s re mote dma re ad/write cach e. when this bit is se t high,remote dma cache control will be enabled. xx :reserved configuration register b (r/w) t o prevent a n y accid ent al w r i t e of this registe r , it is ? hidde n ? behin d a pre v iously unu sed regi ste r . regi ster 0bh in the epcc controller ' s page 0 of regi sters wa s prev iously rese rved on a read. now config uratio n regi ster b can be r ead at that addre ss and ca n be written to by followin g a re ad to 0bh with a write to 0bh. if any other encc co ntroll er regi ste r acce sses t a ke place betwe e n the read an d the write then the write to 0bh will access the remote byte count register 1. 7 6 5 4 3 2 1 0 x x l i n k x x x x i o 1 6 c o n gdlin k phys1 phys0 phys1,0 : physical la yer interf ace 0 0 a u t o d e t e c t 0 1 r e s e r v e d 1 0 1 0 b a s e 5 1 1 1 0 b a s e t in auto detect mode. for TC3299A, ma10 open for 10baset or 10base5 auto-detect. gdlink : when this bit is high, to disabl e link test pulse generation and integrity checking. io16con : whe n this bit is set high the controll er g enerates io1 6 * af ter reg* and ce1* active. if lo w this output is generated only on address decode. l i n k : when this bit is high, link test integr ity checking is goood. otherwise, indicate link signal loss. x x : r e s e r v e d . configuration register c can be load dat a from eeprom only 7 6 5 4 3 2 1 0 x x x x x x x x x x x x crdase l xx crdasel : w hen thi s bit is hig h . crda0, crda1 in crea si ng ad dre s s control by in ternal ca che st ate machine. confidential. 1 1 /26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet when this bit is low , crda0, crda1 increasi ng address control by remote read command. x x : r e s e r v e d . hardw a re configuration thes e func tions are c onfigured during a power on reset . eecfg(ma9) : ma9 should be pulled down to enable cfga and cfgb load from eeprom. auicb(ma10) : in media physic auto detect mode. it should be opened for TC3299A. eng8(ma1 1) : if ma1 1 is pull down and eeprom 03h bit(0) is s e tt ing high, epcc can work at ne2000 8 bit mode. otherwise it will work at 16-bit mode. iosp(ma12) : if ma12 is pull down, en able i/o bas e 300h,32 0 h, 340 h, and 36 0h se p a rately . if ma12 is not pulle d lo w , de spite of the value of pj1, 0, t c 32 99a respon ses to i/o a ccess at the i/o base address 300h, 320h, 340h, and 360h. dcd5bit(ma13) : reg a rdl e ss of ma12 setting, on ce ma13 is pulle d down, tc3 299a only de cod e s in put address sa4 - sa0 and can only work at i/o base address. programming register (r/w) the epcc controller enable sof t ware (driver) programming eeprom or testing interrupt signal through this register directly . it is located at epcc ' s core register page3 base+02h. 7 6 5 4 3 2 1 0 e e s e l x x x x read c s s k d i do(r) a t t r d i s eesel,cs,sk,di,do : the sof t ware can read or prog ram seri al eeprom directly through t hese pins. eesel should be set high before st arting the eeprom read/write. read : epcc ca n rel o a d cf ga,cfg b and inte rn al prom if t h is bit i s set high. when reload st ate is completed, read will be cleared to low . a ttrdis : attribute and common memory access will be disable if it is programmed to high. note : do : read only a ttrdis : write only 3 . 1 e p c c c o r e r e g i s t e r s all regi sters are 8 - bit wid e and m app e d into two p a ges whi c h a r e sel e cte d in the com m a nd regi sters (ps0,ps1). pins a0 -a3 are used to address re gi st ers within each p a g e . page 0 regi ster are those regi sters whi c h are comm only accesse d during epcc controll e r operation while page 1 registe r s a r e use d prim aril y for initializa t ion. the re gi sters a r e p a rt itioned to av oid having to perfo rm two read/ write cycles to access commonly used registers. register assignment s : a0-a3 rd wr page 0 address assignment s (ps1=0,ps0=0) 00h command (cr) command (cr) 01h current local dma address 0 (clda0) page s t art register (pst ar t) 02h current local dma address 1 (clda1) page s t op register (pst op) 0 3 h b o u n d a r y p o i n t e r (bnr y) boundary pointer (bnr y) confidential. 12/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet a0-a3 rd wr 0 4 h t r ansmit s t a t u s register (tsr) t r ansmit page s t art address (tpsr) 05h number of collisions register (ncr) t r ansmit byte count register 0 (tbcr0) 0 6 h f i f o ( f i f o ) t r ansmit byte count register 1 (tbcr1) 0 7 h i n t e r r u p t s t a t u s register (isr) interrupt s t atus register (isr) 08h current remote dma address 0(crda0) remote s t art address register 0 (rsar0) 09h current remote dma address 1 (crda1) remote s t art address register 1 (rsar1) 0ah config. register a (cfga) remote byte count register 0 (rbcr0) 0bh config. register b (cfgb) remote byte count register 1 (rbcr1) 0ch receive s t atus register (rsr) receive configuration register (rcr) 0 d h t a lly counte r 0 (fram e alignme n t errors) (cntr0) t r ansmit configuration register (tcr) 0eh t a lly counter 1 (crc errors) (cntr1) dat a configuration register (dcr) 0fh t a lly counter 2 (missed packet errors) (cntr2) interrupt mas k register (imr) a0-a3 rd wr page 1 address assignment s (ps1=0,ps0=1) 00h command (cr) command (cr) 01h physical address register 0(p a r0 ) physical address register 0(p a r0) 02h physical address register 1(p a r1 ) physical address register 1(p a r1) 03h physical address register 2(p a r2 ) physical address register 2(p a r2) 04h physical address register 3(p a r3 ) physical address register 3(p a r3) 05h physical address register 4(p a r4 ) physical address register 4(p a r4) 06h physical address register 5(p a r5 ) physical address register 5(p a r5) 07h current page register (curr) current page register (curr) 08h multicast address register 0(mar0 ) multicast address register 0(mar0) 09h multicast address register 1(mar1 ) multicast address register 1(mar1) 0ah multicast address register 2(mar2 ) multicast address register 2(mar2) 0bh multicast address register 3(mar3 ) multicast address register 3(mar3) 0ch multicast address register 4(mar4 ) multicast address register 4(mar4) 0dh multicast address register 5(mar5 ) multicast address register 5(mar5) 0eh multicast address register 6(mar6 ) multicast address register 6(mar6) 0fh multicast address register 7(mar7 ) multicast address register 7(mar7) confidential. 13/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet a0-a3 rd wr page 2 address assignment s (ps1=1,ps0=0) 00h command(cr) command(cr) 01h page s t art register (pst ar t) current local dma address 0(clda0) 02h page s t op register (pst op) cu rrent local dma address 1(clda1) 03h remote next pac k e t pointer remote next pac k e t pointer 04h t r ansmit page s t art address(tpsr) reserved 05h local next packet pointer local next packet pointer 06h address counter (upper) address counter (upper) 07h address counter (lower) address counter (lower) 08h reserved reserved 09h reserved reserved 0ah reserved reserved 0bh reserved reserved 0ch receiv e configuration register(rcr) reserv ed 0dh t r ansmit configuration register(tcr) reserved 0eh dat a configuration register(dcr) reserv ed 0fh interrupt mask register(imr) reserved note: page 2 registe r s sho u ld only be accesse d for diagno stic pu rposes. they sho u ld not be modified during normal operation. page 3 re served should never be modified. a0-a3 rd wr page 3 address assignment s (ps1=1,ps0=1) 00h command(cr) command(cr) 01h reserved reserved 02h programming reg. programming reg. 03h reserved reserved 04h reserved reserved 05h reserved reserved 06h reserved reserved 07h reserved reserved 08h reserved reserved 09h reserved reserved 0ah reserved reserved 0 b h r e s e r v e d r e s e r v e d 0ch reserv ed reserv ed 0dh reserv ed reserv ed 0eh reserved reserved 0fh reserved reserved confidential. 14/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet register descriptions: com m a nd register (cr) (read/w rite) the comma n d re giste r is use d to initiat e tran smi ssi o n s, en able o r disa ble remo te dma op erations and to sele ct regi ster p a ge s. t o issue a co mmand th e microprocessor set s the co rrespon ding bit(s) (rd2, rd1, rd0, a nd txp). further co mman d s may be overlapp ed, but with the following rul e s: (1) if a transmit comm and ov erla p s with a remote dma operation, bi t s rd0, rd1, and rd2 mu st be maint a i ned for the remote dma comm and wh en setting th e txp bit. note, if a rem o te dma co mmand i s re-issued wh en giving the transmit comm a nd, the dma will compl e te i mmediately if the remote byte count re gister have not been reini t ialized. (2 ) if a remote dma ope ration overla p s a transmi ssion, rd0, rd1, a nd rd2 may be written wit h the de sire d values a nd a ? 0 ? to this bit has no ef fec t. (3) a remote write dma may not overlap re mo te read operation or visa versa. either of these operatio ns mu st either com p lete or be aborted before the other operation may st art. bi t s ps1, ps0, rd2, and stp may be set any time. 7 6 5 4 3 2 1 0 p s 1 p s 0 r d 2 r d 1 r d 0 t x p st a s t p bit sy mbol description d 0 s t p s t op : sof t ware reset command, t a kes th e controller o f fline , no p a cket s will be received o r transmitted . any recep t ion of transmission in progress will continue to c o mpletion be fore entering the reset st ate . t o e x it this st ate, the stp bit must be reset. the sof t ware reset is e x ecuted on ly when th e rst bit in the isr being set to a 1. stp powers up high. d1 st a s t art: this bit is u s ed to a c tive the epcc co re af t e r either p o wer up, or whe n the epcc co rd ha s been pl ace d in a re set mode by sof t ware command. st a power up low . d 2 t x p t r ansmit pac k et: this b i t must be set to in itiate tran smission o f a p a cket. txp is in ter nally reset e i ther a f ter th e transmissio n is comple ted or aborted. t h i s b i t s h o u l d b e se t o n l y a f t e r t h e t r a n s m i t b y t e c o u n t a n d t r ansmit page s t art registers have been programmed. txp powers up low . d3-d5 rd0-rd2 remote dma comm and: these three encode d bit s control op era t ion of the remote dma ch ann el . rd2 ca n b e set to abou t any remote dma comm and i n prog re ss. th e re mote s t art add r e s se s a r e n o t re st ored to the st arting address if the remote dma is aborted. rd2 powers up high. r d 2 r d 1 r d 0 0 0 0 n o t a l l o w e d 0 0 1 remote read 0 1 0 r e m o t e w r i t e ( n o t e ) 0 1 1 send packet 1 x x a b o r t / c o m p l e t e r e m o t e d m a ( n o t e ) d6,d7 ps0,ps1 page sele ct: thre e two en cod ed bit s se lect whi c h re gister p a g e is to be accessed with addresses a0-3. p s 1 p s 0 0 0 register page 0 0 1 register page 1 1 0 register page 2 1 1 register page 3 dat a configure register (dcr) this re giste r is u s e d to p r og ram th e e p cc fo r 8 or 16-bit memo ry interfa c e s , sele ct byte orde rin g in 16-bit ap plica t ions an d est ablish fifo thre shol ds. th e dcr mu st be initialized prio r to load the rem o te byte count registers. confidential. 15/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 7 6 5 4 3 2 1 0 - f t 1 f t 0 a r m l s - - w t s bit sy mbol description d 0 w t s w o rd t r a n s f e r s e l e c t 0: select s byte-wide dma transfers. 1: select s word-wide dma transfers no te : wh en wo rd-w ide mode is se lec t e d , u p to 32k words ar e a ddr essa ble ; a0 remains low . d 1 - reserv e d d 2 - reserv e d d 3 l s l o o p b a c k s e l e c t 0: loop ba ck mode sel e cted. bit s d1,d2 of the t cr mu st also be programmed for loopback mode selected. 1: normal operation. d 4 a r m auto-initializ e r e m o t e 0: send com m and not ex ecute d , all p a cket s remove d from buf f er ring under program control. 1: send co mmand executed, re mot e dma auto - initialized to remove p a cket s from buf f er ring. d 5 , d 6 f t 0 , f t 1 fif o th re sh ol d s e l e ct: e n co d e d fi fo th re sh ol d. durin g re cept io n, t h e f i fo th resh old in dic a tes the number o f bytes ( o r wor d s) th e f i f o has fille d serially from the network before t he fifo is emptied onto memory bus. receive thresholds f t 1 f t 0 w o r d w i d e b y t e w i d e 0 0 1 w o r d 2 b y t e s 0 1 2 w o r d 4 b y t e s 1 0 4 w o r d 8 b y t e s 1 1 6 w o r d 1 2 b y t e s duri ng tra n smissi on, the fifo thre sho l d indicates t he num ber of bytes (of wo rd s) the fifo ha s filled from the local dma befo r e being transfe rred to the memo ry . thus, the tra n smi ssi on thresh old is 16 bytes less the receive threshold. t r ansmit configuration register (tcr) the tra n smit config uratio n est abli s he s the a c tion s of the tra n smitter se ct ion of the e p cc d u rin g transmission of a acket on the network, lb1 and lb0 power up as 0. 7 6 5 4 3 2 1 0 - - - ofst a t d l b 1 l b 0 c r c bit sy mbol description d 0 c r c i n h i b i t c r c 0: crc appended by transmitter 1: crc inhibited by transmitter d 1 , d 2 l b 0 , l b 1 encod ed l o o pba ck co ntro l: these en coded co nfigu r ation bit s se t the type of loopb ack that sh ou ld be pe rf orm ed. notethat l oopb ack in m ode 2 set s the lpb k pin high, th is pla c e s the tc30 96 in l o opba ck mod e and that d3 of the dcr must be set to zero for loopback operation. confidential. 16/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet bit sy mbol description l b 1 l b 0 mode0 0 0 normal operation (lpbk=0) mode1 0 1 internal loopback (lpbk=0) mode2 1 0 external loopback (lpbk=1) mode3 1 1 external loopback (lpbk=0) d 3 a t d auto t r an sm it disable: t h is bit allows another st at ion to disabl e the epcc ' s tran smitter by tra n smi ssi on of a p a rticul ar m u ltica s t p a cke t. the transmitter can be re-ena bled by reset t i ng this bit o r by re ceptio n of a second p a rticular multicast p a cket. 0: normal operation 1: re ceptio n of multica s t a ddre s s h a shi ng to 6 2 bit d i sabl es t r an smitter , reception of multicast address has hing to bit 63 enables transmitter . d4 ofst colli sion of fset enable: th is bit modifie s the ba ck of f algorithm to allow prioritization of nodes. 0: backof f logic implement s normal algorithm. 1 : forces backo f f a l gor ith m mod i fica tion to 0 to 2 m i m(3+n, 10) sl ot t i me s f o r f i r s t thr e e c o llis i ons , the n fo llows s t a ndar d b a cko f f . (fo r first th ree co llis ions st ation has higher average backof f del ay making a low priority mode.) d 5 - reserv e d d 6 - reserv e d d 7 - reserv e d t r ansmit s t atus register (tsr) this re giste r records event s that occur on the media during tran smissi on of a p a cket. it is cleare d whe n the host initi a tes the nex t transmi ssi o n . all bit s re main low u n l e ss the even t that corre spond s to a p a rti c ula r bit occurs du ring transmi ssi on . each trans missi on sh oul d be followed by a read of this regi ster . the content s of this register are not s pecified until af ter the first transmission. 7 6 5 4 3 2 1 0 o w c c d h f u c r s a b t c o l - p t x bit sy mbol description d0 ptx packet t r an smitted: indica tes tran smi s sion witho u t error (no exce ssive collisions or fifo underrun) (abt= ? 0 ? ,fu= ? 0 ? ). d 1 - reserv e d d2 col t r a n smit coll ided: indicate s t hat the transmi ssi on col lided at least once with another st ation on th e network. the number of collisions i s record ed in the number of collisions registers. (ncr). d3 abt t r a n smit abo r ted: indicate s the epcc aborte d tran smissi on be ca use of excessive collisions. (t ot al number of transmissions including ori g inal transmission attempt equals 16). d 4 c r s carrier sense lost: this b i t is se t when carrier is lost d u ring transmission of the p a cket. carrier sense is monito red from the end o f preamb l e/ synch until txe is dropped. t r ansmission is not aborted on loss of carrier . d5 fu fifo und e rrun: if the epcc cann ot gain acce ss of the bus befo r e the fifo empties, this bit is set. t r ansmission of the p a cket will be aborted. confidential. 17/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet d6 cdh c d h e a r t b e a t : f a i l u r e o f t h e t r a n s c e i v e r t o t r a n s m i t a c o l l i s i o n s i gnal a f ter transmiss i on of a p a ck et will s e t this bit. the c o llis ion detec t (cd) heartbeat si g n a l m u st co mm en ce du ri n g th e fi rst 6.4 u s of th e i n te rf ram e g a p fo ll o w i n g a trans mission . in ce rt a i n co llis io ns , th e cd h ear tb ea t b i t w i ll be s e t e v en though the transceiver is not per forming the cd heartbeat test. d7 owc out of window colli sion: indicate s that a collision occurred af ter a slot time (51.2us). t r ansmissions re scheduled as in normal collisions. receiv e configuration register (rcr) this re giste r determi ne s operatio n of the epcc duri n g re ception of a p a cket and is used to progra m what types of p a c k e t s to ac c ept. 7 6 5 4 3 2 1 0 - - m o n p r o a m a b a r s e p bit sy mbol description d0 sep save errored pac k e t s 0: packet s with receive errors are rejected. 1: packet s wit h receive erro rs are accept ed. receive erro rs a r e crc and frame alignment errors. d1 ar accept runt packet s 0: packet s with fewer than 64 bytes rejected. 1: packet s with fewer than 64 bytes accepted. d 2 a b a c c e p t b r o a d c a s t 0: pac k e t s with all 1 ' s broadcast destination address rejected. 1: pac k e t s with all 1 ' s broadcast destination address accepted. d 3 a m a c c e p t m u l t i c a s t 0: packet s with multicast destination address not checked. 1: packet s with multicast destination address checked. d 4 p r o p r o m i s c u o u s p h y s i c a l 0: physical addre ss o f node mu st match the st ation address programmed in p a r0-p ar5. (physical address checked) 1: a ll p a cket s with any physical add re ss accepte d . (ph y sical a ddress not checked) d5 mon monitor mo d e : enables t he re ceiver t o che c k add resse s and crc o n incomi ng p a cket s witho u t buf fering to memory . the misse d p a cket t a lly counter will be incremented for each recognized p a cket. 0: pac k e t s buf fered to memory . 1: packet s ch ecked fo r ad dre ss m a tch, good crc a nd frame alig nment but not buf fered to memory . d 6 - reserv e d d 7 - reserv e d note: d2 and d3 a r e ? or ' d ? togethe r , i.e., if d2 and d3 a r e se t the epcc wil l accept b r oa dca s t an d multic as t addres ses as well as it s own phy s i ca l address . t o es t a blish full promis cuous (non discrimi nation ) mode, bit s d2, d3 a nd d4 shoul d be set. in addition the multicast ha shin g array mus t be s e t to all 1 ' s in order to accept all multicast addresses. receiv e s t atus register (rsr) confidential. 18/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet this registe r reco rd s st at us of the re ceived p a ck e t, including i n formatio n on errors and the type of address mat c h, either p h ysical o r multicast. the cont ent s of this re gister are written to buf fer memory by the dma af te r re ceptio n of a good p a cket. if p a cket s with errors a r e to be save d the re ceive st atus i s written to memory at the h ead of the erroneo us p a cket if an erron eou s p a cket is received. if p a cket s with errors are to be rej e cted the rs r will not be writte n to memory . the content s will be cl eared when the next p a cket a rrive s. crc e rro rs, fra m e a lignment e rro rs a nd misse d p a cket s a r e counte d internally by the epcc whi c h relinqui she s the host from readin g the rs r in re al time to re cord errors for network management functions. the content s of this register are not specified until af ter the first reception. 7 6 5 4 3 2 1 0 d f r d i s p h y mp a f o f a e c r c p r x bit sy mbol description d 0 prx packet re cei v ed int a ct: indicates p a cket re ceive d without e rro r . (bit s crc, f ae, fo and mp a are zero for the received p a cket.) d1 crc cr c erro r: indic a tes p a c k et rec e iv ed with cr c er r o r . incr ement s t a lly counter (cntr1). this bit will also be set for frame alignment errors. d2 f ae frame alig n m ent error: in dicate s that the incomin g p a cket did no t end on a byte bou n dary a nd the crc di d no t match at la st byte bou ndary . increment s t a lly counter (cntr0). d3 fo fifo overru n: this bit is set whe n the fifo is no t service d causi ng overflow during reception. recept ion of the p a cket will be aborted. d4 mp a missed pa cket: set when p a cket intend ed for node cannot b e a c cepted by epcc be cau s e of a la ck of re ceive buf fers of if the co ntroll er is in monitor mod e and did not buf fer the p a cket to memory . increme n t s t a lly counter (cntr2). d 5 p h y physical/m ultica st address: i ndicate s whether re ceiv ed p a cket h ad a physical or multicast address type 0: physical address match 1: multicast/broadcast address match d 6 d i s re ceiv er di s abled: set whe n receiver di sa bled by enteri ng monitor mode. reset when receiver is re -enabled when exiting monitor mode. d7 dfr deferrin g: set when crs or co l input s are active. if the transceiv er ha s asserte d the cd line a s a result of the jabbe r , this bit will st ay set indicating the jabber condition. note: following coding applies to crc and f ae bit s f ae crc t y pe of error 0 0 no error (good crc and <6 dribble bit s ) 0 1 crc error 1 0 legal, will not occur 1 1 frame alignment error and crc error interrupt mask register (imr) the interru p t mask regi ste r is u s ed to mask interrupt s. eac h interru p t mask bit co rre sp ond s to a bit in the interru pt s t atus regi ster (isr). if an interru pt mask bit is set an i n terrupt will be issue d wh enever the corre s p ondin g bit in the isr is set. if any bit in the im r is set low , an interru pt will not occur wh en the bit in the isr is set. the imr powers up all zeroes. 7 6 5 4 3 2 1 0 - r d c e cnte o vwe t xee rxee p t x e p r x e confidential. 19/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet bit sy mbol description d 0 p r x e packet received interrupt enable: enables interrupt when p a cket received. d1 ptxe packet t r a n smitted interru pt e nable: enable s interrupt when p a cket is transmitted. d2 rxee receive error inte rrupt enable: enabl es inte rrupt when p a cket received with error . d 3 t x e e t r ansmit error interrupt e nable: enables interrupt when p a cket t r ansmission result s in error . d 4 o v w e over w r ite w a rnin g interru pt enable: enable s interrupt wh en buf f er management logic lacks suf f icient buf fers to store incoming p a cket. d5 cnte cou n ter overflow interrupt enable: en a b les inte rrupt whe n msb o f one or more of the network t a lly counters has been set. d6 rdce dma c o mple te interru pt enable: ena b l e s inter r u p t whe n re mot e dma transfer has been completed. d 7 - reserv e d interrupt s t atus register (isr) t h is re gis t er is accesse d to d e t er mine the caus e o f a n inte rrupt. a n y inte rrupt can be ma sked in the i n t e rru p t ma sk re gi st e r (i m r ). in divi du al i n te rrupt bit i s cle a r ed by writ in g a ? 1 ? i n to th e co rre s p o n d i ng bi t of the is r. t h e ir q s i gna l is ac tive as lo ng as a n y u n masked sign al is se t, and w i ll no t go low un til a l l unmarke d b i t s i n this register have been cleared. the isr must be cl eared af ter power up by writing it with all 1 ' s. 7 6 5 4 3 2 1 0 r s t r d c c n t o v w t x e r x e p t x p r x bit sy mbol description d0 p r x p a cket receiv ed: i ndicat e s p a cket receiv ed wit h no errors. d1 ptx packet t r ansmitted: indicates p a cket transmitted with no errors. d2 rxe re ceive erro r: indicates th at a p a cket was re ceived with on e o r m o re of the following errors: - crc error - frame alignment error - fifo overrun - missed p a cket d3 txe t r a n smit error: set when p a cket tran smitted with one or more of th e following errors: - excessive collisions - fifo underrun d 4 ovw over w r ite w a rnin g: set whe n re ceiv e buf fer ring stora ge re source s have been exhausted. (local dma has reached boundary pointer). d5 cnt cou n ter ove r flow: set wh en msb of o ne or more o f the network t a lly counters has been set. d6 rdc remote dm a complete: set when re mote dma o peratio n ha s been completed. d7 rst reset s t atus: a st atus indicator with no interrupt generated - set when epcc ente r s re set st ate and is clea red when a st art command is issued - set wh en a re ceive buf f er ring over fl ows an d is cl eare d when leaves overflow st atus. w r iting to this bit has no ef fect and powers up high. confidential. 20/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet netw ork t a lly counter registers (cntr) thre e 8-bit counters a r e p r ovided fo r m onitorin g the numbe r of crc e r rors, frame alignme n t errors a nd missed p a cket s , the maximum cou n t rea c he d by any counte r is 192 (c0h). these re gisters will be cleared when read by the cpu. the count is recor ded in binary in ct0-ct7 of each t a lly register . cntr0: monitor the number of frame alignment error 7 6 5 4 3 2 1 0 c t 7 c t 6 c t 5 c t 4 c t 3 c t 2 c t 1 c t 0 cntr1: monitor the number of crc error 7 6 5 4 3 2 1 0 c t 7 c t 6 c t 5 c t 4 c t 3 c t 2 c t 1 c t 0 cntr2: monitor the number of missed packet s 7 6 5 4 3 2 1 0 c t 7 c t 6 c t 5 c t 4 c t 3 c t 2 c t 1 c t 0 number of collisions register (ncr) this regi ster cont ain s the numbe r of col lision s a no de experien c e s whe n attempt i ng to tran smi t a p a cket. if no colli sions are experienced duri ng a transmission attempt, the col bit of the tsr will be set and the content s of ncr will be zero. if ther e are excessive collisions, the abt bit in the tsr will not be set and the content s of ncr will be zero. the ncr is cleared af ter the txp bit in the cr is set. 7 6 5 4 3 2 1 0 - - - - n c 3 n c 2 n c 1 n c 0 fifo register (fifo) this is an 8 - b i t register that allows the cpu to exam ine the content s of the fifo af ter loop ba ck. the fifo will cont ai n th e last 8 dat a bytes tra n smi tted in the loo pba ck p a cket . sequential read s from th e fifo will advan ce a pointer in the fifo and allow reading of a ll 8 bytes. note that the fif o shoul d only be read when the epcc has been programmed in loopback mode. 7 6 5 4 3 2 1 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 phy s ical address registers (p ar0-p ar5) the physi cal addre s s re gisters are use d to comp are the destinati on add re ss o f incoming p a cket s for reje cting or a c cepting p a cket s. com p arison s are pe rformed on a byte-wid e ba sis. the bit assi gnme n t shown below relates the sequence in p a r0-p ar 5 to the bit sequence of the received p a cket. . . s y n s y n d a 0 da1 d a2 da3 d a4 da5 d a 6 d a 7 . . |------- desti nationaddress --------|-- source d7 d6 d5 d4 d3 d2 d1 d0 p a r 0 d a 7 d a 6 d a 5 d a 4 d a 3 d a 2 d a 1 d a 0 p a r 1 d a 1 5 d a 1 4 d a 1 3 d a 1 2 d a 1 1 d a 1 0 d a 9 d a 8 p a r 2 d a 2 3 d a 2 2 d a 2 1 d a 2 0 d a 1 9 d a 1 8 d a 1 7 d a 1 6 p a r 3 d a 3 1 d a 3 0 d a 2 9 d a 2 8 d a 2 7 d a 2 6 d a 2 5 d a 2 4 p a r 4 d a 3 9 d a 3 8 d a 3 7 d a 3 6 d a 3 5 d a 3 4 d a 3 3 d a 3 2 p a r 5 d a 4 7 d a 4 6 d a 4 5 d a 4 4 d a 4 3 d a 4 2 d a 4 1 d a 4 0 confidential. 21/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet multicast address registers (mar0-mar70) the multicast address registers provide filtering of multicast add resses hashe d by the cr c logic. all destination ad dresses are fed through th e crc logic a nd as the last bit o f the destination addres s enters the crc, the 6 most sign ificant bit s o f the c rc generator are la tched. these 6 bit s are then deco ded b y a 1 o f 64 decode to index a uniq u e filter b i t (f b0- 63) in the multic ast address register . if the filter b i t selec t ed is set, the multicast p a cket is acc epted. the s ystem designe r w ould use a program to de termine which filter bit s to set in the multicast reg i ster s. for some address found to hash to the va lue 50 (32h), then f b 50 in mar6 should be initialized to ? 1 ? . all mu lticast filter b i t s tha t correspond to multicast a ddress accep t ed b y th e node are then set to one. t o accept all multicast p a cket s all of the registers are set to all ones. d7 d6 d5 d4 d3 d2 d1 d0 m a r 0 f b 7 f b 6 f b 5 f b 4 f b 3 f b 2 f b 1 f b 0 m a r 1 f b 1 5 f b 1 4 f b 1 3 f b 1 2 f b 1 1 f b 1 0 f b 9 f b 8 m a r 2 f b 2 3 f b 2 2 f b 2 1 f b 2 0 f b 1 9 f b 1 8 f b 1 7 f b 1 6 m a r 3 f b 3 1 f b 3 0 f b 2 9 f b 2 8 f b 2 7 f b 2 6 f b 2 5 f b 2 4 m a r 4 f b 3 9 f b 3 8 f b 3 7 f b 3 6 f b 3 5 f b 3 4 f b 3 3 f b 3 2 m a r 5 f b 4 7 f b 4 6 f b 4 5 f b 4 4 f b 4 3 f b 4 2 f b 4 1 f b 4 0 m a r 6 f b 5 5 f b 5 4 f b 5 3 f b 5 2 f b 5 1 f b 5 0 f b 4 9 f b 4 8 m a r 7 f b 6 3 f b 6 2 f b 6 1 f b 6 0 f b 5 9 f b 5 8 f b 5 7 f b 5 6 dma registers local dma transmit registers 1 5 8 | 7 0 ( t p s r ) t r a n s m i t pa g e st ar t (tbcr0,1) transmit byte count local dma receive registers 1 5 8 | 7 0 (pst ar t ) p a ge st ar t (pst o p ) p a ge st o p ( c u r r ) c u r r e n t ( b r n y ) b o u n d a r y 1 5 8 | 7 0 (clda0,1) current local dma address remote dma registers 1 5 8 | 7 0 ( r s a r 0 , 1 ) s t ar t a d d r e s s ( r b c r 0 , 1 ) b y t e c o u n t (crda0,1) current remote dma address confidential. 22/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet (i) local dma t r ansmit registers t r ansmit p age st art register (tpsr): this regi ster point s to the assembl ed p a cket to be t r ansmitted. o n ly the eight highe r o r de r addresse s a r e specified ince all transmit p a cket s are assembled on 256-byte p age boundaries. 7 6 5 4 3 2 1 0 a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 t r ansmit byte count register0,1 (tbcr0,tbcr1): these two re gisters indi cat e the l ength o f the p a cket to be tran smitt ed in bytes. the maximum numbe r of transmit bytes allowed is 64k bytes. the epcc w ill not truncate transmissions longer than 1500 bytes. 7 6 5 4 3 2 1 0 t b c r 1 l 1 5 l 1 4 l 1 3 l 1 2 l1 1 l 1 0 l 9 l 8 7 6 5 4 3 2 1 0 t b c r 0 l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 (ii) local dma receiv e registers page st art, stop registers (pst ar t , st op): the page s t art and pa ge stop regi ste r s p r og ram th e st a r ting an d stoppi ng p a ge of the re ceive buf f er ring. since the epcc use s fixed 256-b y te buf fers a ligned on p age bounda rie s only the upper eight bit s of the st art and stop address are specified. 7 6 5 4 3 2 1 0 pst ar t pst op a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 boundary register (bnr y): this regi ster is used to prevent overflo w of the re ceive buf f er ri ng. buf f er managem ent co mp a r e s the conte n t s of this re giste r to the next buf fer addre s s whe n linkin g buf fers together . if the content s of this register match the next buf fer address the local dma operation is aborted. 7 6 5 4 3 2 1 0 bnr y a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 (iii) remote dma registers remote s t art address registers (rsar0,1): remote byte count registers (rbcr0,1): remote dma operation s a r e p r og ramm ed via the remote s t a r t addre s s (rs a r0,1) and remote byte cou n t (rb c r0,1) re giste r s. the rem o te s t art addre ss is used to po int to the st art of the block of dat a to be transferred and the remote byte count is used to indicate the length of the block (in bytes). 7 6 5 4 3 2 1 0 r s a r 1 a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 7 6 5 4 3 2 1 0 r s a r 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 confidential. 23/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 7 6 5 4 3 2 1 0 r b c r 1 b c 1 5 b c 1 4 b c 1 3 b c 1 2 bc1 1 bc10 b c 9 b c 8 7 6 5 4 3 2 1 0 r b c r 0 b c 7 b c 6 b c 5 b c 4 b c 3 b c 2 b c 1 b c 0 current page register: the buf f er manag ement l ogic u s e s this regi ster inte r nally; it is used as a ba ckup regi ster fo r reception. curr cont ai ns the addre ss of the first buf fer to be us e d for a p a cket receptio n and is use d to restore dma pointe r s in the event of receive errors. thi s r egi ster is initialized to the same value as pst ar t and should not be written to again unless the controller is reset. 7 6 5 4 3 2 1 0 c u r r a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 current local dma register 0,1 (clda0,1): these two registers can be accessed to det ermine the current local dma address. 7 6 5 4 3 2 1 0 c l d a 1 a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 7 6 5 4 3 2 1 0 c l d a 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 current remote dma address registers: the cu rrent remote dma regi sters co nt ain the cu rrent addr ess o f the remote dma. the bit assignm ent is shown below: 7 6 5 4 3 2 1 0 c r d a 1 a 1 5 a 1 4 a 1 3 a 1 2 a1 1 a 1 0 a 9 a 8 7 6 5 4 3 2 1 0 c r d a 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 confidential. 24/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet 4 absolute maximum ratings ambient tempera t ure under bias 0 c to 70 c st orage tempera t ure -40 c to 125 c vol t age on all input and outputs with respect t o vss -0.5v t o 7v 5 s t andard t est conditions the ch ara c te ristics belo w apply for the following st a ndard test co ndition s. unl e ss otherwise noted. all volt ages are referred to vss (0v ground), posit ive current flows into the referred pin. opera t ing tempera t ure range 0 c to 70 c power suppl y vol t age 4.75v t o 5.25v 6 d.c. characteristics sy mbol parameter min. ty p . max. unit s conditions vil input low vol t age vss - 0.8 v vcc= 5v vih input high vol t age 2.0 - vcc v vcc= 5v iil input low current - - -0.5 ua vin=1.0v iih input high current - - 20 ua vin=vcc vol output low vol t age - - 0.4 v iol=8.0ma voh output high vol t age 2.4 - - v ioh= 4.0ma i c c suppl y c u r r e n t - 3 5 - m a v c c = 5 v confidential. 25/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30
TC3299A preliminary dat a sheet confidential. 26/26 august 27, 20003 copyright ? 2003, i c p l u s c o r p . t c 3299a-ds-r30 7 phy s ical dimensions ? ? ?? ? ????????? ? ? ? ? ? ? ? ? ?? ?? ???? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ??a? ?????? a ?? ?? ?? ?? ??? ??? ??? ?? ?? ?? ? ??? ??? ??? ???? ???? ?? ??? ??? ?? ??? ?? ?? ?? ???? ???? ???? ??? ??? ? ??? ?? a ?? ???? ??? ??? ???? ?? ?? ?? ?? ???? ? ???? ?? ??? ?? ?? ???? ??? ??? ???? ??? ??? ?? ???? ???? ? ? ??? ??? ???? ???? notice information i n this do cu me nt is subje c t t o ch ang e with out notice. icplus reserv es the rig h t s t o ch ang e it s prod uct s at a n y time. therefore, the cu stome r is c a u t ioned to con f irm with icp l us rega rdin g the late st released version before placing orders. icplus devi c e s are no t design ed, intende d, author i z ed, or warra n ted to be suit able for use in life-supporting applications. ic plus corp. h e a d q u a r t e r s s a l e s o f f i c e 10f , no.47, lane 2, kwang-fu road, sec. 2, 4f , no. 106, hsin-t ai-w u road, sec.1, hsin-chu city , t a iwan 300, r.o.c. hsi-ch ih, t a ipei hsien, t a iwan 221, r.o.c. tel : 886-3-575-0275 f a x : 8 8 6 - 3 - 5 7 5 - 0 4 7 5 t e l : 886-2-2696-1669 f a x : 886-2-2696-2220 w ebsite : www . i cplus. com. t w

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